Record Beta
Defect and Fault Tolerance in VLSI [and Nanotechnology] Systems
https://id.confref.org/data/confref-portal/event/dft2017
This record is part of the confref event IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017.
| rdf:type | portal:Conference |
|---|---|
| schema:location | Cambridge (wd:Q350) |
| rdfs:label | Defect and Fault Tolerance in VLSI [and Nanotechnology] Systems |
| portal:acronym | DFT |
| portal:area | https://id.confref.org/data/confref-portal/area/2 |
| portal:city | Cambridge |
| portal:country | UK |
| portal:endDate | 2017-10-25 |
| portal:name | Defect and Fault Tolerance in VLSI [and Nanotechnology] Systems |
| portal:portalPage | http://portal.confref.org/list/dft2017 |
| portal:series | https://id.confref.org/data/confref-portal/series/dft |
| portal:startDate | 2017-10-23 |
| portal:submissionExtended | false |
| portal:year | 2017 |
| cr:discipline | computer science (wd:Q21198) |
| cr:field | Computer and information sciences (https://id.confref.org/data/oecd-fos/1.2) |
| cr:sameAs | https://dblp.org/db/conf/dft/dft2017 |
Beta confref labs is under development. Identifiers are stable; pages, data and services can change.