# https://id.confref.org/data/confref-portal/event/vlsi-soc2018 (confref labs, beta)
@prefix cr: <https://id.confref.org/ontology/> .
@prefix portal: <https://id.confref.org/data/confref-portal/vocab/> .
@prefix rdfs: <http://www.w3.org/2000/01/rdf-schema#> .
@prefix schema: <http://schema.org/> .
@prefix wd: <http://www.wikidata.org/entity/> .
@prefix xsd: <http://www.w3.org/2001/XMLSchema#> .

<https://id.confref.org/data/confref-portal/event/vlsi-soc2018>
    a portal:Conference ;
    schema:location wd:Q2028 ;
    rdfs:label "IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip" ;
    portal:acronym "VLSI-SoC" ;
    portal:area <https://id.confref.org/data/confref-portal/area/2> ;
    portal:city "Verona" ;
    portal:country "Italy" ;
    portal:endDate "2018-10-10"^^xsd:date ;
    portal:keyword "Arithmetic circuits" ,
        "BCH code" ,
        "Circuit layout" ,
        "Clock and data recovery" ,
        "Craig interpolants" ,
        "Design-For-Test" ,
        "Domain specific architecture" ,
        "Dynamic signaling" ,
        "Error Correcting Code" ,
        "FPGA" ,
        "Fanout" ,
        "FinFET" ,
        "Graph mapping" ,
        "Gröbner bases" ,
        "HW/SW co-design" ,
        "Hard problems" ,
        "Heuristics" ,
        "High-Level Synthesis" ,
        "Logic synthesis" ,
        "crossbar" ;
    portal:name "IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip" ;
    portal:portalPage <http://portal.confref.org/list/vlsi-soc2018> ;
    portal:series <https://id.confref.org/data/confref-portal/series/vlsi-soc> ;
    portal:startDate "2018-10-08"^^xsd:date ;
    portal:submissionExtended "false"^^xsd:boolean ;
    portal:year "2018"^^xsd:integer ;
    cr:discipline wd:Q21198 ;
    cr:field <https://id.confref.org/data/oecd-fos/1.2> .