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System Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings

Name: System Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings
Start: 2015-11-03
End: 2015-11-06
Location: Foz do Iguaçu

IESS

Date: 2015-11-03/06
Place: Foz do Iguaçu, Brazil on the map
Series: International Embedded Systems Symposium
Edition: 5
Academic field: Natural sciences: Computer and information sciences
Disciplines: computer science
Identifier: https://id.confref.org/event/e11bc5h

Proceedings

Title	DOI	Year	Record
System Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings IFIP Advances in Information and Communication Technology 523	10.1007/978-3-319-90023-0	2017	dblp

Sources

The records of the sources that this identifier brings together (cr:sameAs).

confref portal (2020)	`https://id.confref.org/data/confref-portal/event/iess2015` · page
dblp	`https://dblp.org/db/conf/iess/iess2015`

Cite

System Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings. confref identifier e11bc5h. https://id.confref.org/event/e11bc5h

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