Event Beta

VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers

Name: VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers
Start: 2008-10-13
End: 2008-10-15
Location: Greece

VLSI

Date: 2008-10-13/15
Place: Greece
Series: IEEE/IFIP International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SOC)
Edition: 16
Academic field: Natural sciences: Computer and information sciences
Disciplines: computer science
Identifier: https://id.confref.org/event/e11ybjg

Proceedings

Title	DOI	Year	Record
VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers IFIP Advances in Information and Communication Technology 313	10.1007/978-3-642-12267-5	2010	dblp

Sources

The records of the sources that this identifier brings together (cr:sameAs).

confref portal (2020)	`https://id.confref.org/data/confref-portal/event/vlsi2008` · page
dblp	`https://dblp.org/db/conf/vlsi/vlsisoc2008s`

Cite

VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers. confref identifier e11ybjg. https://id.confref.org/event/e11ybjg

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