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VLSI Design and Test

https://id.confref.org/data/confref-portal/event/vdat2018

This record is part of the confref event VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers.

rdf:typeportal:Conference
schema:locationMadurai (wd:Q228405)
rdfs:labelVLSI Design and Test
portal:acronymVDAT
portal:areahttps://id.confref.org/data/confref-portal/area/2
portal:cityMadurai
portal:countryIndia
portal:endDate2018-06-30
portal:keyword2D architecture
portal:keyword3D
portal:keywordADS
portal:keywordAES
portal:keywordAHIR
portal:keywordANN and PSO
portal:keywordActuation voltage
portal:keywordAngular steiner tree
portal:keywordApproximate computing
portal:keywordCMOS
portal:keywordFPGA
portal:keywordLeakage current
portal:keywordLeakage power
portal:keywordNetwork-on-Chip
portal:keywordPropagation delay
portal:keywordRouting
portal:keywordStacking effect
portal:keywordTFT
portal:keyworda-IGZO TFT
portal:keywordnetwork on chip
portal:nameVLSI Design and Test
portal:portalPagehttp://portal.confref.org/list/vdat2018
portal:serieshttps://id.confref.org/data/confref-portal/series/vdat
portal:startDate2018-06-28
portal:submissionExtendedfalse
portal:year2018
cr:disciplinecomputer science (wd:Q21198)
cr:fieldComputer and information sciences (https://id.confref.org/data/oecd-fos/1.2)
cr:sameAswd:Q106245327
cr:sameAshttps://dblp.org/db/conf/vdat/vdat2018

Data: Turtle · JSON-LD · N-Triples · RDF/XML

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