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VLSI Design and Test

https://id.confref.org/data/confref-portal/event/vdat2017

This record is part of the confref event VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers.

rdf:typeportal:Conference
schema:locationRoorkee (wd:Q1020718)
rdfs:labelVLSI Design and Test
portal:acronymVDAT
portal:areahttps://id.confref.org/data/confref-portal/area/2
portal:cityRoorkee
portal:countryIndia
portal:endDate2017-07-02
portal:keyword3D IC
portal:keywordBCD
portal:keywordCMOS
portal:keywordCTAT
portal:keywordDWT
portal:keywordEnergy efficiency
portal:keywordEquivalence checking
portal:keywordFPGA
portal:keywordField Programmable Gate Array (FPGA)
portal:keywordFinFET
portal:keywordLow power
portal:keywordPTAT
portal:keywordPVT compensation
portal:keywordReliability
portal:keywordSRAM
portal:keywordSoC
portal:keywordTCAD
portal:keywordautomotive
portal:keywordfault tolerance
portal:keywordformal verification
portal:nameVLSI Design and Test
portal:portalPagehttp://portal.confref.org/list/vdat2017
portal:serieshttps://id.confref.org/data/confref-portal/series/vdat
portal:startDate2017-06-29
portal:submissionExtendedfalse
portal:year2017
cr:disciplinecomputer science (wd:Q21198)
cr:fieldComputer and information sciences (https://id.confref.org/data/oecd-fos/1.2)
cr:sameAswd:Q106245328
cr:sameAshttps://dblp.org/db/conf/vdat/vdat2017

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